A CMOS 4-PAM Multi-Gbps Serial Link Transceiver A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE OF GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

As the demand for higher data-rate communication increases, low-cost, high-speed serial links using copper cables become attractive for distances of 1 to 10 meters. For multi-Gbps applications, the data rate is limited by the channel low-pass characteristics due to cable skin-effect loss and the speed of the process technology. This design uses a receiver equalizer in combination with a transmitter filter to compensate for the channel low-pass characteristics. The target channel is a 10-meter copper coaxial cable with a -3dB bandwidth of <1GHz. A 4-level pulse amplitude modulation (4-PAM) is used to reduce the symbol rate to half that of the conventional 2PAM system. This symbol rate reduction decreases the required channel bandwidth for proper data transmission by a factor of two and also allows the designer to halve the onchip clock frequency. High on-chip frequencies are further lowered by multiplexing and demultiplexing the data directly at the chip pads. This design also takes advantage of a new proportional phase detector for 4-PAM data recovery at multi-Gbps rates. This PLL does not suffer from the stability and bandwidth limitations of traditional bang-bang loops